The integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs.
Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. For example, as semiconductor device features become closer in proximity to one another, so do the respective contact elements providing a connection to the device features. Forming these tightly constrained and often of significant height features can raise processing challenges. These process margins can be further tightened during FinFET fabrication processes. In particular, decreasing fin pitches and increasing fin heights are significantly constraining abilities of existing processes for forming contact features to source and drain or gate features of the FinFET device. Accordingly, although techniques have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects.